1. Field of the Invention
The present invention relates to a clock synchronization of devices with different clocks and, more particularly, to an apparatus and method for synchronizing two devices with different operation clocks (referred to as ‘clock’, hereinafter).
2. Background of the Related Art
In general, when a clock ratio between a RAM (e.g., an SDRAM (Synchronous Dynamic Random Access Memory)) and a memory controller of a microprocessor is a ratio of 2:1, a clock speed of the RAM is regulated to slow down to have the same speed as the clock speed of the microprocessor. This helps synchronize the clock ratio to 1:1 in spite of an interface between the synchronous devices.
If the clocks of each device to be interfaced do not agree with each other, the clock of a device with a fast clock speed must be lowered down to the level of the clock of a device with a slow clock speed for the purpose of interfacing. Therefore, the related art method for synchronizing the clock between two devices having a different clock has a problem that a maximum performance of the device with a fast clock speed is degraded as much as the clock speed is lowered.